This invention relates generally to radio receiver frequency control systems and more particularly to an automatic frequency control (AFC) for a single sideband receiver to be used at frequencies designated for land mobile services.
In a single sideband radio system, the tolerable frequency error without significant loss of voice recognition or intelligibility is approximately .+-.20 Hz. Traditional means of controlling radio frequencies such as crystal frequency standards cannot alone maintain this close tolerance at frequencies greater than approximately 20 MHz. Typical crystal oscillator performance over the temperatures encountered in a mobile radio environment ranges from .+-.5 parts per million (ppm) to .+-.1 ppm. The cost of the .+-.1 ppm oscillator is inherently much greater than that of a .+-.5 ppm oscillator. Considering a VHF frequency of 150 MHz, these tolerances yield frequency errors of .+-.750 Hz and .+-.150 Hz respectively.
To resolve this frequency tolerance problem, continuous phase locked loop (PLL) techniques have been widely adopted among single sideband receiver designers Generally, PLL receiver AFC circuits are realized in a loop that includes a first mixer, an intermediate frequency (IF) filter and gain, product detector with associated reference oscillator, a loop filter, and a voltage controlled oscillator (VCO) which in turn accepts a frequency control voltage from the loop filter and produces the local oscillator (LO) signal for the first mixer. The received SSB signal is demodulated by the product detector. The received signal, which may incorporate a frequency error, is correctly located in the IF filter bandpass by means of the natural acquisition characteristics of the PLL. However, such a continuously controlled PLL exhibits a potential for degrading the adjacent channel interference performance as a result of noise which may be present on the VCO control line due to on-channel modulation or adjacent-channel interference. Various methods, such as dual-bandwidth and split loop techniques have been proposed to diminish the loop noise; however, these AFC techniques described previously may have further shortcomings such as poor demodulator performance when the received signal is subject to multipath signal propagation or inferior acquisition performance. For these reasons, the received AFC to be disclosed in further detail herein employs a directed frequency sweep of the LO in conjunction with a "short loop" phase-locked SSB demodulator following the IF filter and gain in order to maximize demodulator performance in a multipath signal environment, to ensure rapid frequency acquisition, and to eliminate LO noise problems.
Classical frequency sweep schemes utilize a low sweep frequency, usually less than one-half the square of the steady state detector PLL natural frequency, thereby permitting enough time for the acquisition and centering of the received signal or low signal levels. At this sweep frequency, however, the time to simply acquire and center the desired signal with the AFC loop becomes unacceptably long (up to 250 msec) and adds to the receiver squelch operation time such that the initial segments of the message may be lost.
In such classical sweep schemes, a lock detector is commonly used to determine when the desired signal, converted to an IF frequency by the swept local oscillator, falls within a predetermined window around the "centered" position in the IF bandpass. When the signal reaches this window, the local oscillator sweep is terminated and any remaining frequency error is typically irnored. The speed of the lock detector is important in acquiring lock; a slow lock indication may allow the signal to sweep past the centering window and not be centered while a fast lock indication may allow perturbations, like noise, to break lock or cause the detector to fail in initially acquiring the signal.
These conflicting lock detector requirements are reconciled by means of a dual time constant lock detector having the time required to sense the lock condition of the PLL significantly shorter than the time required to sense the unlock condition of the PLL. When this lock detector is utilized to control the sweep, squelch activation can begin before centering of the received signal is fully complete, thereby minimizing the time required for activation of the squelch.
It can be appreciated, then, that previous AFC circuits have required a series of compromises to enable their operation. The present invention enables independent optimization of the key AFC parameters and enables single sideband receivers to approach the performance of well-established frequency modulation receivers.